In general, an image sensor refers to a semiconductor device for converting an optical image into an electrical signal. Image sensors can be classified as a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor. The CCD image sensor includes metal-oxide-silicon (MOS) capacitors that are formed very close to each other, where charge carriers are stored in and transferred from the capacitors.
Meanwhile, a CMOS image sensor is a device employing a switching mode to sequentially detect an output by providing MOS transistors corresponding to the number of pixels through a CMOS technology that uses peripheral devices, such as a control circuit and a signal processing circuit.
A charge coupled device (CCD) has various disadvantages such as a complicated drive mode and high power consumption. Also, the CCD requires many steps of mask processes, making the process for the CCD complicated, and it is difficult to integrate a signal processing circuit onto a single chip of the CCD. Recently, to overcome these disadvantages, CMOS image sensors using a sub-micron CMOS manufacturing technology have been studied and developed.
The CMOS image sensor includes a photodiode and a MOS transistor in each unit pixel to sequentially detect the signal by switching mode, thereby realizing the images. Since the CMOS image sensor makes use of the CMOS manufacturing technology, the CMOS image sensor has low power consumption and simplifies the manufacturing process thereof. That is, the CMOS sensor manufacturing process can be achieved by using about 20 masks, while the CCD process requires 30 to 40 masks. Also, many signal processors can be integrated onto a single chip of the CMOS image sensor, so the CMOS image sensor is spotlighted as a next-generation image sensor. Accordingly, the CMOS image sensor is used in various applications such as digital still camera (DSC), PC camera, mobile camera and so forth.
Meanwhile, the CMOS image sensors are classified as 3T-type, 4T-type, or 5T-type CMOS image sensors in accordance with the number of transistors formed in a unit pixel. The 3T-type CMOS image sensor includes one photodiode and three transistors, and the 4T-type CMOS image sensor includes one photodiode and four transistors. Hereinafter, description will be made in relation to a layout of a unit pixel of the 3T-type CMOS image sensor.
FIG. 1 is an equivalent circuit view of the common 3T-type CMOS image sensor, and FIG. 2 is a layout view illustrating the unit pixel of the common 3T-type CMOS image sensor.
As shown in FIG. 1, the unit pixel of the common 3T CMOS image sensor includes one photodiode PD and three nMOS transistors T1, T2 and T3. A cathode of the photodiode PD is connected to the drain of the first nMOS transistor T1 and the gate of the second nMOS transistor T2.
In addition, the sources of the first and second nMOS transistors T1 and T2 are connected to a power line that feeds a reference voltage VR, and the gate of the first nMOS transistor T1 is connected to a reset line that feeds a reset signal RST.
Also, the source of the third nMOS transistor T3 is connected to the drain of the second nMOS transistor T2, the drain of the third nMOS transistor T3 is connected to a reading circuit (not shown) through a signal line, and the gate of the third nMOS transistor T3 is connected to a column select line that feeds a selection signal SLCT.
Therefore, the first nMOS transistor T1 is referred to as a reset transistor Rx, the second nMOS transistor as a drive transistor Dx, and the third nMOS transistor T3 as a selection transistor Sx.
As shown in FIG. 2, an active area 10 is defined on the unit pixel of the common 3T CMOS image sensor, so that one photodiode 20 is formed in a large-width part of the active area 10, and gate electrodes 120, 130 and 140 of three transistors are formed overlapping the remaining parts of the active area 10.
That is, the reset transistor Rx incorporates the gate electrode 120, the drive transistor Dx incorporates the gate electrode 130, and the select transistor Sx incorporates with the gate electrode 140.
Here, dopants are implanted into the active area 10 of each transistor, excluding below lower portions of the gate electrodes 120, 130 and 140, thereby forming a source and drain area of each transistor.
Thus, a power supply voltage Vdd may be applied to the source/drain area formed between the reset transistor Rx and the drive transistor Dx, and the source/drain area formed at one side of the select transistor Sx is connected to a reading circuit (not shown).
Although not shown in the drawings, the gate electrodes 120, 130 and 140 are connected to the signal lines for Rx, Dx, and Sx, respectively. Each signal line has a pad at one end thereof, and is connected to an external driving circuit.
FIG. 3 is a sectional view showing a conventional CMOS image sensor.
As shown in FIG. 3, an isolation area and an active area having a photodiode area and a transistor area are defined on the P++ type semiconductor substrate 100, and a P− type epitaxial layer 101 is grown on the semiconductor substrate 100. Then, a field oxide layer 102 is formed on the isolation area of the semiconductor substrate 100 to separate the input areas of green, red and blue light, and an N− type diffusion area 103 is formed on the photodiode area of the semiconductor substrate 100.
Thereafter, gate insulating layers 104 and gate electrodes 105 are formed on the transistor area of the semiconductor substrate 100, and insulating sidewalls 106 are formed at both sides of the gate electrode 105. Then, a diffusion barrier 107 is formed on the gate electrode 105.
Then, a first interlayer dielectric layer 108 is formed on the diffusion barrier 107, and various metal interconnections 109 are formed on the first interlayer dielectric layer 108. The metal interconnections 109 are spaced apart from each other by a predetermined interval.
In addition, a second interlayer dielectric layer 110 having a thickness of about 4000 Å is formed on the entire surface of the semiconductor substrate 100, including the metal interconnections 109, and a first planar layer 111 is formed on the second interlayer dielectric layer 110. Then, the red (R), green (G) and blue (B) color filter layers 112 are formed on the first planar layer 111 corresponding to each N− type diffusion area 103.
The color filter layers 112 include three colors of R, G and B, in which the boundaries thereof are always overlapped or the thickness of the three color filters are non-uniformly formed.
In other words, as shown in FIG. 3, the R color filter layer has the largest thickness and the G color filter layer has the smallest thickness.
In addition, a second planar layer 113 is formed on the entire surface of the semiconductor substrate 100 including the color filter layers 112, and the microlenses 114 are formed to correspond to each color filter layer 112.
Here, reference numeral 115, not yet described, is a source and drain impurity area of the transistor.
However, the conventional CMOS image sensor described above has the following problem.
That is, the color reproduction of blue (B) wavelength is lower than that of other wavelengths, so that, in extreme case, a greenish effect occurs.
The greenish effect refers to a phenomenon incurring an afterimage of green color in the display even though the green color is shifted from the display.
The greenish effect may occur because the green color wavelength reacts prior to the blue color wavelength. To solve this problem, it is necessary to efficiently make the light reaction of the blue color wavelength.